Your GPU is running at x8 and nothing is wrong — but the register can't tell you that

By Daniel S. · July 14, 2026

TL;DR: Three of us spent a night reseating GPUs, reading slot tables and arguing about root complexes to explain why two cards were running at PCIe x8. The answer was one line: the RTX 5060 Ti is a native x8 card. Eight lanes, by design, on every model. The x16 connector is mechanical — half the pins aren't wired. The reading was correct, healthy, and expected the entire time. And the genuinely nasty part, the reason this is a post and not a tweet: the register reading for "healthy native x8" is identical to the reading for "a real x16 card that has failed down to x8." The hardware cannot tell you which one you have.

The card is x8. All of them are.

The RTX 5060 Ti (GB206) has a PCIe 5.0 x8 host interface. Not a downgrade, not a slot problem, not a reseat away from being fixed. The full-length x16 edge connector is mechanical only — it's shaped to fit an x16 slot, and half the data lanes are simply not electrically connected.

This is the tier norm, not a quirk of one model. Since Ada, the x60-class parts have shipped x8:

x8 is the correct reading. No slot on Earth raises it. If you have one of these cards and nvidia-smi says x8, stop looking — you are done, and you were done before you started.

Why you didn't just look this up

Because NVIDIA does not publish the lane count. Their own RTX 5060-family spec table lists the interface as "PCI Express Gen 5" — Gen 5, no lane count, nothing else. The vendor page you would naturally check will not tell you the number you need. That is the whole reason a room full of people who know what they're doing lost a night to this.

For lane counts, use the TechPowerUp GPU database, which lists Bus Interface: PCIe 5.0 x8 for this card, and has a dedicated review of x8 scaling on it. ⏱️ verified 2026-07-12

Write the lane count down somewhere your future self will find it. It is not on the box, and it is not on the manufacturer's page.

The trap: the register reports two different things at once

Here's where it stops being a trivia question. Run this on a 5060 Ti:

nvidia-smi -q | grep -A2 'Link Width'
#   Max: 16x
#   Current: 8x

Max 16x, current 8x. Every troubleshooting reflex you have says that's a downgraded link, go find the fault.

It isn't. What's happening is that the two halves of that reading are answering different questions about different pieces of hardware:

• LnkCap (the "Max") reports the SILICON. The GPU die's PCIe controller is capable of x16, and it says so.
• LnkSta (the "Current") reports the BOARD. The add-in card's PCB wires eight lanes and stops.

The chip advertises sixteen. The card delivers eight. Both readings are true, and the "downgrade" you're staring at happened at the factory.

Therefore LnkCap x16 / LnkSta x8 is also the exact signature of a real, genuine fault on a card that actually is x16 — a bad reseat, a dirty slot, a link that trained badly.

The register does not discriminate. Only the card's spec does.

This is why the tempting shortcut — writing "x8 downgraded is fine, ignore it" in your notes — is the wrong lesson to take away, and I'd argue actively dangerous. Adopt that rule and you will wave through the one time it means something, on the 3090 in the next slot over.

The correct rule: the expected width can only come from the card's documented spec. Not from the register, not from the slot table, not from the other card in the box.

What this does to your acceptance test

If you gate hardware with a script — and if you're building a multi-GPU box you should — this has a sharp consequence: a link-width check cannot derive its own expectation from the hardware. There's no clever query that yields the right answer, because LnkCap will confidently tell you "16" about a card that is physically eight lanes.

Your gate has to compare the observed width against a number you looked up and wrote down. In mine that's literally a constant, sourced from the spec sheet:

EXPECT_WIDTH=8    # from the card's documented spec, NOT from LnkCap

Ugly? A bit. It's also the only thing that can be correct.

The one width failure that is real

There is a documented link-training bug on the 5060 Ti where the card comes up at x1, x2 or x4 instead of x8 — varying from boot to boot — reproduced across MSI, Gainward and ASUS samples, and fixed by a host BIOS update. Not a dead card, not the slot. ⏱️ verified 2026-07-12

So the acceptance criterion falls out cleanly:

• Trained at x8 → PASS. Stop looking. This is the card working.
• Trained below x8 (x1/x2/x4) → REAL. Go fix it, starting with the motherboard BIOS.
• "x8 but I wanted x16" → not a criterion, and never was.

And because that bug varies per boot, one good width reading is not proof of anything. If it matters to you, check it across several boots.

While you're here: your slots are lying to you too

The other half of that lost night was slot geometry, and it's worth thirty seconds.

On the workstation I was building, all six PCIe connectors are physically x16-sized. Two of them are electrically x8 (and rated 25W instead of 75W). A GPU drops straight into an eight-lane slot with a satisfying click and no complaint whatsoever. That is how the trap is set — the connector tells you nothing about the wiring behind it.

Two sources will tell you the truth before you ever open the case:

1. The manufacturer's slot table — PSREF, the maintenance manual, the motherboard manual. It lists electrical width per slot.
2. The BIOS bifurcation options, which on my box agreed slot-for-slot: the x16 slots offer x4x4x4x4 / x8x8 / x16, and the x8 slots only offer x8 / x4x4. A slot whose firmware won't even offer x16 is not wired for sixteen lanes.

Two independent, agreeing, pre-boot sources — both of which we had on file, and both of which we ignored in favor of pulling cards out of a machine at midnight.

Does x8 actually cost you anything?

Sometimes. Do the arithmetic instead of feeling anxious about it:

• On a Gen5 host, the 5060 Ti's Gen5 x8 gives you ~31.5 GB/s per direction — exactly the same bandwidth as Gen4 x16. The x8 is genuinely free. This is why NVIDIA could ship it.
• On a Gen4 host (my workstation is one), you only negotiate Gen4 speeds, so Gen4 x8 is ~15.75 GB/s — half the card's rated host bandwidth. That loss is real.

Whether real means relevant depends entirely on the workload:

• Loading models and running llama.cpp with a layer split across cards: effectively irrelevant. Host-link bandwidth costs you a few seconds of model load; inference traffic between layers is tiny.
• Tensor-parallel serving, where cards exchange activations every token: now it matters, and it's worth designing around.

Know which one you're doing before you spend money to fix a number.

What the night actually cost

Nobody was careless. We had the vendor slot table on file. We had the BIOS options in front of us. We derived, reasoned, cross-checked and reseated our way to a conclusion, when the entire question was answered by one line on a spec page nobody read — because the obvious place to look, the manufacturer's own product page, does not print the number.

The fix wasn't "be more rigorous." It was writing the fact down in a file, with a grade on it saying whether we measured it or merely inferred it, so the next person retrieves it in five seconds instead of re-deriving it at midnight.

We're excellent at deriving facts and nearly incapable of retrieving them. A fact you filed and can't find is operationally the same as a fact you never had.